The present invention relates generally to arbitration in computer systems. More particularly, the invention is directed to systems and methods for arbitrating access to shared resources in a pseudo-round-robin format which provides fairness and a high rate of throughput.
Arbiters and the functions they perform have become commonplace in contemporary computer systems. This is particularly true in the context of multiple processor architectures where the control of data traffic between the processors, the memory system and input/output (I/O) units is an important aspect of the overall computer system design. The arbiter plays a critical role because it decides which elements get access to a data path in the system, whether that data path is over a shared bus or through a crossbar switch. The goal is to minimize the delay in the arbitration while satisfying the fairness standard defined by a protocol.
Though fixed priority arbiters are simple in design, they do not ensure fairness. Requesters with high priority can monopolize the shared resource by continuing to request service and always prevailing over lower priority requesters in the arbitration.
Round-robin type arbiters ensure fairness in the access to the shared resources while providing good throughput. As to the latter feature, a well designed round-robin arbiter immediately serves any pending request, if one exists. Maximum throughput to the shared resource requires that the grant of access be resolved, in the same clock cycle, if access is possible. This is in contrast to time slot allocation type of servicing of access requests.
Unfortunately, known same cycle response type round-robin arbiter architectures do not lend themselves to efficient circuit implementation, either in terms of electronic device count, semiconductor area or speed. Furthermore, conventional round-robin architecture detractions grow linearly in relation to the units potentially requesting access.